Browsing by Subject "Data flow analysis"

Now showing items 1-14 of 14

    • Article  

      CacheFlow: Cache optimizations for data driven multithreading 

      Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro (2006)
      Data-Driven Multithreading is a non-blocking multithreading model of execution that provides effective latency tolerance by allowing the computation processor do useful work, while a long latency event is in progress. With ...
    • Article  

      Data-driven multithreading using conventional microprocessors 

      Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro (2006)
      This paper describes the Data-Driven Multithreading (DDM) model and how it may be implemented using off-the-shelf microprocessors. Data-Driven Multithreading is a nonblocking multithreading execution model that tolerates ...
    • Article  

      Data-Driven Thread Execution on Heterogeneous Processors 

      Arandi, Samer; Matheou, George; Kyriacou, Costas; Evripidou, Paraskevas (2017)
      In this paper we report our experience in implementing and evaluating the Data-Driven Multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the ...
    • Conference Object  

      Data-flow vs control-flow for extreme level computing 

      Evripidou, Paraskevas; Kyriacou, Costas (Institute of Electrical and Electronics Engineers Inc., 2014)
      This paper challenges the current thinking for building High Performance Computing (HPC) Systems, which is currently based on the sequential computing also known as the von Neumann model, by proposing the use of Novel ...
    • Article  

      Exploiting course grain parallelism from FORTRAN by mapping it to IF1 

      Lachanas, Adrianos; Evripidou, Paraskevas (1998)
      FORTRAN, a classical imperative language is mapped into IF1, a machine-independent dataflow graph description language with Single Assingment Semantics (SAS). Parafrase 2 (P2) is used as the front-end of our system. It ...
    • Article  

      Improving branch prediction by considering affectors and affectees correlations 

      Sazeides, Yiannakis; Moustakas, Andreas; Constantinides, Kypros; Kleanthous, Marios M. (2011)
      This work investigates the potential of direction-correlations to improve branch prediction. There are two types of direction-correlation: affectors and affectees. This work considers for the first time their implications ...
    • Article  

      Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform 

      Diavastos, Andreas; Trancoso, Pedro; Luján, M.; Watson, I. (2016)
      The introduction of multi-core processors has renewed the interest in programming models which can efficiently exploit general purpose parallelism. Data-Flow is one such model which has demonstrated significant potential ...
    • Article  

      Mapping fortran programs to single assignment semantics for efficient parallelization 

      Evripidou, Paraskevas (1998)
      This paper presents Mustang, a system that automatically parallellizes Fortran programs by mapping them to single assignment semantics. Specifically, sequential Fortran source programs are translated into IF1, a ...
    • Article  

      A multimedia programming model based on timed concurrent constraint programming 

      Papadopoulos, George Angelos (1998)
      We propose the development of multimedia programming frameworks based on the declarative logic programming setting and in particular the framework of object-oriented timed concurrent constraint programming (OO-TCCP). The ...
    • Article  

      Rapid prototyping of the data-driven chip-multiprocessor (D 2-CMP) using FPGAs 

      Tatas, Konstantinos; Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro; Wong, S. (2008)
      This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that ...
    • Article  

      The significance of affectors and affectees correlations for branch prediction 

      Sazeides, Yiannakis; Moustakas, Andreas; Constantinides, Kypros; Kleanthous, Marios M. (2008)
      This work investigates the potential of direction-correlations to improve branch prediction. There are two types of direction- correlation: affectors and affectees. This work considers for the first time their implications ...
    • Conference Object  

      The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices 

      Solinas, M.; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Girbal, S.; Goodman, D.; Khan, B.; Koliai, S.; Li, F.; Luján, M.; Morin, L.; Mendelson, A.; Navarro, N.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Valero, M.; Weis, S.; Watson, I.; Zuckermann, S.; Giorgi, Roberto (2013)
      Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably ...
    • Article  

      TERAFLUX: Harnessing dataflow in next generation teradevices 

      Giorgi, Roberto; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Gayatri, R.; Girbal, S.; Goodman, D.; Khan, B.; Koliaï, S.; Landwehr, J.; Lê, N. M.; Li, F.; Lujàn, M.; Mendelson, A.; Morin, L.; Navarro, N.; Patejko, T.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Watson, I.; Weis, S.; Zuckerman, S.; Valero, M. (2014)
      The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been ...
    • Conference Object  

      TFluxSCC: Exploiting performance on future many-core systems through Data-Flow 

      Diavastos, Andreas; Stylianou, Georgios; Trancoso, Pedro (Institute of Electrical and Electronics Engineers Inc., 2015)
      The current trend in processor design is to increase the number of cores as to achieve a desired performance. While having a large number of cores on a chip seems to be feasible in terms of the hardware, the development ...